As known in the semiconductor art, demand continues to increase for sub-micron semiconductor devices with high density, high performance, and ultra large-scale integration. These semiconductor devices require increased speeds, high reliability, and increased manufacturing throughput. As the semiconductor device geometries continue to decrease, the conventional semiconductor technologies are challenged in forming gate dielectric layers.
Conventional semiconductor devices comprise a substrate having various electrically isolated regions, called active regions, in which individual circuit components are formed. The active region typically includes source and drain regions of a transistor formed in the semiconductor substrate, spaced apart by a channel region. A gate electrode for switching the transistor is formed on the channel with a gate dielectric layer isolating the gate electrode and the substrate. The quality and thickness of the gate dielectric are crucial for the performance and reliability in the finished integrated circuit (IC) device.
Furthermore, the speed of circuit components, such as MOS transistors, is affected by the time required to charge and discharge parasitic load capacitances in a circuit. Since a lower operating voltage leads to a shorter time of charging and discharging the load capacitances, faster circuitry is therefore typically obtained. In order to reduce the operating voltage, however, the threshold voltage of the transistor must also be lowered. One way to lower the threshold voltage is to reduce the thickness of the gate dielectric layer, which contributes proportionately to the body effect and hence, the threshold voltage.
As mentioned above, the reliability of a transistor is also affected by the thickness of its gate dielectric. For example, if an excessive potential is applied to the gate electrode, the gate dielectric may break down and cause a short circuit, typically between the gate electrode and the source. The potential at which the gate dielectric breakdown occurs is termed the “breakdown voltage,” which is related to the thickness of the gate dielectric. Since the gate dielectric layer must be thick enough to prevent a breakdown, a higher operating voltage necessitates a thicker gate dielectric to support a higher breakdown voltage.
As known in the art, semiconductor devices may have circuit components operating at different voltages within the same IC. For example, a microprocessor may include speed-critical components that are operated at lower voltages (e.g., 1.0 V to 1.2 V), and may also contain less speed-critical components that operate at higher operating voltages (e.g., 1.5 V to 2.0 V). Transistors utilizing a low operating voltage (e.g., 1.2 V) may have a thinner gate dielectric layer (typically 31 Angstroms), while transistors with higher operating voltages (e.g., 1.5 V) may have a thicker gate dielectric layer (typically 61 Angstroms). This increase in the gate dielectric thickness makes the gate dielectric less susceptible to a breakdown.
Input/output (I/O) buffer circuits typically need to translate an input operating voltage to a higher or lower operating voltage. Conventional buffer architectures may include higher voltage, thick-gate dielectric transistors to implement buffers for safe operation, yet such buffers suffer from low performance, particularly at lower voltage levels of the chip. On the other hand, conventional buffer architectures may include thin-gate dielectric transistors, which are smaller and significantly faster but which are unable to withstand the higher voltage levels and, as a result, may not be reliable.
There is a need for methods, devices, and systems to enhance the operation of buffers. Specifically, there is a need for a buffer configured to tolerate higher external operating voltages while meeting performance specifications.